MicroConsult Academy GmbH

MicroConsult Academy GmbH

Overview Arm®v8 Real Time Profile

Cortex® R52 Processor Architecture

Instruction Sets

Synchronization and Barriers

• Exclusive Monitors

Writing C for Arm

Exceptions and Handling

• Exception Levels

• Interrupts and Aborts

• Interrupt Controller Architectures

• Routing and Trapping

• Nesting and Returning

Timer

• Generic Timer

• Performance Monitor Unit

Internal Connectivity and Memory

• Bus Interfaces

• Tightly Coupled Memory and Caches

• Performance Aspects

Memory Protection Unit

• Purpose and Use Cases

• Regions and Attributes

Safety Aspects

• Register Protection

• Indirect Memory Access

• Dual Core Lockstep

• ECC

• Error Reporting

Debug and Tracing

Virtualization

• Use Cases

• Hypervisor

• Temporal and Spatial Separation

• Identification

• Asynchronous Stimuli

Exercises

HINWEIS: Die Kursunterlagen sind auf Englisch