Super-junction MOSFETs Influence of parasitic components in switching behavior

The faster switching of the power MOSFETs enable higher power conversion efficiency. However, parasitic components in the devices and boards are involving switching characteristics more as the switching speed is getting faster. This creates unwanted side effects, like high voltage or current spikes or poor EMI performance.

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MEV Elektronik Service GmbH

Power MOSFET technology has been developed towards higher cell density for lower on-resistance. There are, however, silicon limits for significant reduction in the on-resistance with the conventional planar MOSFET technology because of its exponential increase in on-resistance according to the increase of blocking capability. One of efforts to overcome the silicon limit is super-junction technology in high-voltage power MOSFETs.

The super-junction technology can dramatically reduce both on-resistance and parasitic capacitances, which usually are in trade-off. With smaller parasitic capacitances, the super-junction MOSFETs have extremely fast switching characteristics and reduced switching losses. However, fast transitions in voltage and current result in high-frequency noises and radiated EMI.

To achieve low noise radiation, high values of parasitic capacitances are required. There is direct conflict in parasitic capacitance requirements. Based on recent system trends, improving efficiency is a critical goal and going with slow switching device just for EMI is not an optimized solution. In part 1, we will discuss about influence of parasitic components to achieve balance between these considerations when designing with super-junction MOSFETs.

Influence of Circuit Parameters on Switching Characteristics

Package & Layout Parasitics: To drive fast-switching super-junction MOSFETs, it is also necessary to understand the influence of the prasitics in package and PCB layout on switching performance. The super-junction MOSFETs are mainly used in the voltage range of 500-600 V. In these voltage ratings, the most popular packages are industry standard TO-220, TO-247, TO-3P, and TO-263. The impact of the package on performance is limited due to the fact that the internal gate and source bonding wire length are fixed.

Only the length of the lead can be changed to reduce the source inductance of the package. Typical lead inductance of 10 nH, as shown in Figure 1(a), doesn’t look like much, but a turn-off a current with di/dt=500 A / µs is easily possible with these MOSFETs. The voltage across this inductance is V_IND = 5 V and, with a turn-off di/dt of 1,000 A / µs, the induced voltage is V_IND = 10 V.

This short calculation shows that the complete source inductance, not only the lead inductance of the package, must be reduced to acceptable value. Another source of noise is layout parasitic. Two types are visible: parasitic inductance and parasitic capacitance. 1 cm of trace pitch has an inductance of 6-10 nH, which can be reduced by adding one layer on the topside of the PCB and a GND plane on the bottom side of the PCB.

The other type is the parasitic capacitances. Figure 1(b) shows the principles of capacitive layout parasitics. The capacitance between one trace is immediately over the other trace or GND plane on the other side of the PCB. The second one is the capacitance built up between the device and the GND plane. Two parallel traces on both sides of PCB increase capacitance, but also reduce the inductance of the loop, resulting in less magnetic noise radiation.

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