Influence of parasitic components in switching behavior

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MEV Elektronik Service GmbH

Effect of parasitic Inductance

Inductances and current loops have an influence on performance in any given application. Currents run in a loop and create a magnetic field. If a change in the current occurs, the magnetic field changes and creates an inductive voltage, V_L. With Faraday’s law, the value of V_L can be calculated by:

Therefore, L depends also on the geometry of the loop. If the change in the current (di/dt) is stable, but higher inductance comes from the bigger area of current loop, V_L increases. Enclosed current loops with high di/dt values should be minimized. The source and gate inductance must be minimized to avoid poor EMI and switching oscillation. To explain the impact of parasitic inductances, L_G and L_S, in a power MOSFET and layout, turn-off transient switching behavior is simulated using analytical PSPICE simulation.

Figure 2 shows the PSPICE simulation waveforms of the gate-to-source voltage, V_GS; the internal gate-to-source voltage, V_{GS_int}; the drain-to-source voltage, V_DS; the current channel of MOSFET, I_channel; and the drain current, I_D, in clamped inductive load switching circuit. To explain the effect of parasitic inductances of the power MOSFET, the turn-off transient is divided into two intervals (t₁~t₂). Figure 3 shows the MOSFET equivalent circuit including parasitic inductances.

During Time Interval t₁: The voltage V_GS decreases exponentially due to discharging of input capacitance, which the gate-to-source capacitance, CGS, and the gate-to-drain capacitance, C_GD, via the gate resistance, R_g, as shown in Figure 3(a). When the gate voltage reaches the gate plateau voltage, the channel current in the MOSFET is reduced due to output characteristics in MOSFET, which is a characteristic curve between the gate voltage and drain current. At the same time, the output capacitance is charged up slowly.

During Time Interval t₂: The C_oss of the SJ MOSFET becomes strongly non-linear, these effects give an extremely fast dv/dt and di/dt, as shown in Figure 2. At the same time, the voltage drop across the common-source inductance L_S is caused by negative drain current slope (-di_D/dt). This voltage drop leads to negative gate voltage. Due to this effect, the discharged current flows in the opposite direction, as shown in Figure 3(b). In this time, this equivalent circuit can be expressed as R-L-C series resonance circuits.

Two different values of gate inductance are compared in a clamped inductive load switching circuit. A circuit with a low value for L_G has lower peak gate negative voltage (△V_GSA). A circuit with a high L_G value shows much higher peak gate negative voltage (△V_GSB), as shown in Figure 4. To achieve optimized gate waveform, Designer should reduce gate inductance LG and common-source inductance L_S.

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