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Super-junction MOSFETs

Influence of parasitic components in switching behavior

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External Parasitic Coupling Drain-Source Capacitances

Figure 5) MOSFET Equivalent, Including Parasitic Coupling Capacitance
Figure 5) MOSFET Equivalent, Including Parasitic Coupling Capacitance
(Image Source: Fairchild)

External coupling Cgd is one of the root causes for ringing affected by the device and PCB layout. Figure 5 shows the MOSFET equivalent circuit, including resonant circuit with coupling gate-drain capacitance. External gate-drain capacitance is coupled through parasitic inductances, leading to resonance, causing gate oscillation with gate and drain inductance when MOSFET switching speed is fast. It could lead to the gate oscillation at turn-on and turn-off, destruction of gate oxide, or out–of-control or poor EMI performance. External coupling Cgd must be reduced as much as possible to reduce gate oscillation. The capacity between traces can be calculated by Equation (2):

Fig. 6 a) Single Layer: Layout Example with Increased External Cgd
Fig. 6 a) Single Layer: Layout Example with Increased External Cgd
(Image Source: Fairchild)
Fig. 6 b) Double-Layer: Layout Example with Increased External Cgd
Fig. 6 b) Double-Layer: Layout Example with Increased External Cgd
(Imgage Source: Fairchild)

Figure 7a) and 7b) Layout Example with reduced External Cgd
Figure 7a) and 7b) Layout Example with reduced External Cgd
(Image Source: Fairchild)
(Image Source: Fairchild)

Figure 6 shows layout examples with high external Cgd and figure 7 shows layout solutions with reduced external Cgd. The difference in oscillations is shown in Figure 8. VGS (green line) and VDS (magenta line) are during turn off. The experimental waveforms show the effect of the high and low external Cgd in a given layout. The oscillation effect can be forced by increasing the output power level or decreasing the input voltage at the same output power. This can also occur after an AC line drop out: when line voltage is back, the boost stage charges up the bulk capacitor to nominal voltage.

Figure 8a) Turn-Off Waveforms by Different External Cgd
Figure 8a) Turn-Off Waveforms by Different External Cgd
(Image Source: Fairchild)
Figure 8b) Turn-Off Waveforms by Different External Cgd
Figure 8b) Turn-Off Waveforms by Different External Cgd
(Image Source: Fairchild)

During the time when the MOSFET turns off, the drain current is quite high. The drain current commutates to the output capacitance, Coss, of the MOSFET and charges it up to DC bus voltage. The voltage slope is proportional to the load current and inversely proportional to the value of the output capacitance. The value of Coss is high at low VDS and low at high VDS. As a result, dv/dt values of drain-source voltage change during turn-off. The high dv/dt values lead to capacitive displacement currents due to all the parasitic capacitances.

Conclusion: The faster switching of the power MOSFETs enable higher power conversion efficiency. However, parasitic components in the devices and boards are involving switching characteristics more as the switching speed is getting faster. This creates unwanted side effects, like high voltage or current spikes or poor EMI performance. To achieve balance, it is important to optimize gate drive circuitry and minimize parasitic inductances and capacitances on PCB board.

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