Designing advanced DSP applications on the Kinetis Cortex-M4 MCU

For all mathematical operations within discussed application only one fixed-point format has been selected: Q0.15 or Q0.31, that means all numbers are within the <-1,1) interval. This is the fractional format as it is known from the DSP processors and controllers. The main benefit is that the multiplication is never saturated or overflowed, but care must be taken for addition and multiply-accumulate instructions. Proper scaling of the quantities has to be chosen. Also, the selection of a single number representation format for all computations avoids rescaling (shifting) of the values between particular calculations.

As for all fixed-point integer machines, the operation of multiplication has to be followed by arithmetical shift right when operands are of fractional format. There are more ways to emulate the fractional MAC instruction. Here signed multiplication followed by single arithmetic shift left and saturating addition was used.

Example of using intrinsic functions

One of the equations from the Back-EMF observer demonstrates the use of intrinsic functions, supported by the IAR C/C++ compiler:

register int q31tmp;

...

udtIObsrv = __SMULBB(udtIObsrv, f16IScaled);

udtIObsrv = udtIObsrv >> 15;

q31tmp = __SMULBB(f16UScaled, pudtUdq);

q31tmp = q31tmp << 1;

udtIObsrv = __QADD16(q31tmp, udtIObsrv);

Machine cycles and execution time

For the performance of the microcontroller, the machine cycles needed for execution of the fast control current loop (50 to 200 µs) are relevant. Execution of slow speed control loop (1 – 5 ms) can be neglected for evaluation of the CPU load. Picture 2 shows the machine cycles needed for the calculation of the whole control loop.

For better illustration, the aggregated value is divided to particular functions, so it can be seen how much load they represent. Figure 3 then shows the CPU load derived from the execution time that is needed for calculating the algorithm. The listed values of the execution time assume that the program is running from program RAM. It is obvious, that even for 50 MHz CPU speed there is enough margin of CPU power that can be used for the rest of the application.

Operation constraints at CPU speed higher than 36 MHz

Microcontrollers from the Kinetis family are equipped with dual-bank program flash memory. Its access time is 28 ns that is 36 MHz. The flash memory controller contains 64-bit pre-fetch speculation buffer and small 32x 64-bit cache. The speed of the flash memory has to be considered, when the designer wants to operate the MCU at higher frequencies (up to 96 - 120 MHz, depending on the Kinetis subfamily).

If the code is linear (no branches) there are no wait states inserted, that means, the execution speed will not be affected. But at a branch, the data from the cache must be flushed and loaded again from the new address. Thus, the wait states are inserted during the program execution and the CPU speed is considerably affected.

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