An Alternative Cost-Effective Design Flow for Mixed-Signal ASICs

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MEV Elektronik Service GmbH

Cadlog Group

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EDA Solutions Ltd

If it’s a modest requirement, then Tanner EDA has an excellent low-cost tool for basic place-and-route requirements, which is in the sub-100k gate region and for circuits where timing-driven layout is not critical. For example, if it’s a digital design in a 0.18-micron process, running at 5MHz, and the gate and routeing delays are perhaps a few nanoseconds, it’s not really an issue. But if the design is operating at hundreds of megahertz and above, then the delays become significant, potentially leading to logic errors.

A second option, if it’s a more exacting requirement, is to use a design services company or the target foundry to provide this service. For two or three designs per year, for example, it’s perhaps tens of thousands of Euros annually, compared to the several hundreds of thousands of Euros for an annual license for the tools from the leading vendors. There are many well-known and respected companies such as Europractice and IC Mask Design that provide cost-effective place-and-route services.

Analogue Design Flow

Moving to the analogue design flow, essentially this follows the traditional approach: schematic entry; simulation via spice; and full-custom layout, although this include some semi-automated tasks. It’s necessary to go through the schematic entry and simulation loop a few times to ensure correct operation of the circuit.

Following sign-off, the schematic design is passed through to analogue layout, which automatically generates all the basic components in the schematic, such as MOSFETs, resistors and capacitors, so all the designer has to do is the place and route.

Tanner’s highly productive HiPer DevGen layout tool also features an advanced acceleration program that will identify and automatically generate key circuit elements, such as resistor dividers, current mirrors or differential pairs, with a wide range of additional constraint information, such as matching, automatic dummy or antenna diode insertion, ensuring that any process-related effects are taken into account.

Top-Level Layout and Co-Simulation

The top-level layout brings together the analogue and digital in a single chip, with connectivity information extracted from the layout to verify correct performance of the overall circuit. The post-layout analogue and mixed-signal (AMS) co-simulation has the analogue circuits simulated in spice and the digital circuits simulated in the VHDL or Verilog simulator.

A Tanner interface tool provides the handshaking between the two domains. The overall top-level simulation will only run as fast as the slowest simulator, but it should run in a reasonably good timeframe, assuming a fast digital simulator for hundreds of thousands of digital gates, and a good analogue simulator working on a few hundred analogue transistors.

Verification

Once circuit performance is established, full chip verification is run including LVS (Layout Versus Schematic) for both the analogue and digital, top-level verification to ensure everything is connected correctly, and DRC (Design Rule Checking) to confirm the chip is ready for manufacture at the target foundry. Once chip manufacturability is satisfied, the GDSII can be sent to the fab.

This design flow is, of course, true of any vendor’s tools. What we are doing at EDA Solutions is offering an alternative design flow that is low-cost and highly productive, in addition to offering world-class point tools to the mainstream mixed-signal design community.

* * Paul Double ... is Managing Director of EDA Solutions.

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