An Alternative Cost-Effective Design Flow for Mixed-Signal ASICs

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MEV Elektronik Service GmbH

Cadlog Group

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Maintenance is a relatively small percentage of the original license, so design teams can easily budget for the longer term. In addition, companies obtain security of product. For example, if five years after initial production they need to do a re-spin of the design, then they know the same tools will still be available, and at no extra expense.

The important point is to recognize there is an alternative to time-based licensing, so that customers have the flexibility to choose the most suitable licensing model for their projects and budgetary constraints.

Digital Simulation

So what might an ASIC design flow (see Fig. 1) driven by low-cost tools actually look like? Starting with digital simulation, a compelling choice is the Riviera-PRO RTL simulation engine from Aldec Inc., which is a lower-cost, but no-less-functional, alternative to those available from the big players. Running under both 64-bit Windows and Linux, Riviera-PRO supports the main design flows being used in Europe for analogue, digital and mixed-signal designs.

A multi-platform, high-performance, mixed-language RTL and gate-level simulator, the tool includes advanced debugging and support of advanced verification methodologies with SystemC and SystemVerilog, Assertions Based Verification (ABV), Transaction Level Modelling (TLM) and VHDL/Verilog Design Rule Checking (DRC).

Digital Synthesis

Following completion of the digital design and simulation, the next step is synthesis, where a similar case can be made for the availability of cost-effective tools. However, in addition to providing the basic synthesis functionality with the DesignCraft logic synthesis tool from Incentia Design Systems, the tool also offers a host of add-ons to make a world-class design flow.

DesignCraft supports standard gate library formats and allows designers to turn RTL code into gate-level VHDL or Verilog, and also offers the integrated capability to optimize for area, power, timing, and design-for-testability (DFT), in addition to the scan path insertion function.

The timing and power analysis and optimization tools from Incentia, in particular, are best-in-class tools, setting timing constraints and delivering power optimization at the synthesis level, which can lead to a significant reduction in consumption, using clock gating for example, which greatly reduces the power footprint following placing and routing. It is not a stretch to say that the Incentia’s ECOCraft-Power can achieve better power consumption performance than those from some of the leading tool providers.

The Incentia tools are proven for many designs in technologies down to 40nm and gate counts of more than 50 million, which is more than required by most mixed-signal ASIC designers who are developing mixed-signal ASICs in 0.35- to 0.13-micron processes, perhaps down to 90nm, and working in gate counts of a few million devices.

Digital Place and Route

Digital place-and-route is a function that can be executed very efficiently in isolation. A gate-level netlist can be run through a place-and-route tool providing the physical layout and a timing file for re-simulation, to verify that the timing still works following layout. And because the function is very portable, there are a couple of low-cost options for design teams.

Next page: Analogue Design Flow

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