Software design challenges for real-time multicore MCU systems

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MicroConsult Microelectronics Consulting & Training GmbH

DR. JOHANNES HEIDENHAIN GmbH

ISH Ingenieursozietät GmbH

Impact of memory architecture on multicore software design

Two types of memory architectures for code and data memory are available for the new multicore microcontrollers:

Multicore memory architecture type 1:

• less CPU-local (private) memory:
  Level 1: High performance access

• much global system (shared) memory: Level 2: Lower performance competitive access

Multicore memory architecture type 2:

• much CPU-local (private) memory:
  Level 1: High performance access

• less global system (shared) memory:
  Level 2: Lower performance competitive access

The speed of CPU access to on-chip memory involves the response times. To boost software performance, CPU private caches and SRAMs are available to improve access times for code and data. The processing time of interrupt service routines (ISRs) may be one of the most time critical aspects of embedded real-time software. If the program and variables of an interrupt service are accessible without wait states, the ISRs can be performed very fast. Thus, the nesting of interrupt processing means shorter accumulated access delay for lower priority interrupt services.

What is tricky about multicore architectures is that each CPU has its own interrupt and trap controller. Consequently, software de-
signers have to assign the interrupt sources, like peripherals or error events, to a specific CPU-private interrupt vector table. The assignment has to be performed based on the timing requirements of the specific interrupt source.

Memory assignment in multicore architectures

In multicore architectures, real-time and memory protection requirements may be the basis for fixed memory assignment in order to guarantee (worst-case) process timing and correct programming of the memory protection unit (MPU). The software architect assigns code and data to specific memory spaces. Time critical memory can be placed in core private memories, and non time critical information may be placed in global memory.

This design step has an impact on the coding of the source code, because customized section names for memory sections are needed. The user-defined section names can be generated by compiler controls in the C-source files for code (program functions) and data (variables and constants). The project build process includes a compilation of all source files and linking plus locating of the resulting memory sections to the available memory spaces.

The section base addresses in the memory and memory ranges can be user-defined in the project linker description file. The resulting link/locate protocol is stored in a map file that may be the basis for controlling the planned memory architecture.

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