FPGA Design Software Evolution

Anbieter zum Thema

MEV Elektronik Service GmbH

BFP Associates

Lattice GmbH

Improved Design Flow

Three key improvements to the design flow have been made for timing analysis, simulation export and Tcl scripting. The new Timing Analysis view (Figure 4) offers an easy to use graphical environment for navigating timing information. Selecting a constraint provides the ability see the timing paths, detailed paths and path schematic views.

A key new benefit in the new Timing Analysis view is that timing constraints can be changed and the analysis re-run without having to update the implementation. This can save hours on each timing analysis for very large designs.

Another improvement is the export of designs to simulators through the new Simulation Wizard. The Simulation Wizard guides users through all the necessary steps to export a design to a simulator in the format desired, such as simulating the RTL design or the gate-level timing design.

The Diamond software adds new capabilities for scripting the design flow. Diamond-specific Tcl command dictionaries are available for projects, netlists, HDL code checking, power calculation, and hardware debug insertion and analysis. In addition to the Tcl console in the Diamond environment, a separate Tcl console application allows scripts to run independent of the full GUI. Finally, Tcl scripts can be run directly from a DOS or other command shell as commands once the correct setup has been completed, as shown in the example below.

Example 1 – Running Diamond Tcl Script from a DOS Shell

set %LSC_INI_PATH%=

set %LSC_DIAMOND%=true

set %TCL_LIBRARY%=C:\lscc\diamond\1.0\tcltk\lib\tcl8.4

set %FOUNDRY%=C:\lscc\diamond\1.0\ispFPGA

set %PATH%=%FOUNDRY%\bin\nt;%PATH%

C:\lscc\diamond\1.0\bin\nt\pnmainc.exe project.tcl > output.txt

A new generation of PLD design tools

FPGAs are now being used for a broad array of applications and tasks, so the ability to explore alternative implementations is key. A new generation of design tools is doing just that, and the Lattice Diamond design environment is among the first to address the challenges of contemporary FPGA design. Diamond features design exploration, ease of use, improved design flow, and numerous other enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results.

Lattice Diamond is available as a download from the Lattice website for both Windows and Linux. Once downloaded and installed, it can be used with either a free license or a subscription license. The free license provides access to many popular Lattice devices such as MachXO and LatticeECP2 at no cost.

A subscription license can be purchased which adds support for all Lattice FPGAs including the latest LatticeECP3 devices. Both licenses include Synopsys Synplify Pro for Lattice synthesis and Aldec Active-HDL Lattice Edition II mixed language simulator.

* * Brian Caslis ... is a Senior Software Product Planning Engineer at Lattice Semiconductor

(ID:25016850)