How an Algorithm Separates Jitter Components
A new signal model based algorithm from Rohde & Schwarz precisely separates jitter components, giving deep insights during debugging and characterization of high speed signal transmissions.
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The rising data rates and shrinking voltage levels on digital interfaces, the complexity and density of advanced designs, and the cost pressure on board material, connectors and components are driving the need for jitter component analysis.
One way to characterize the total jitter of an interface is to measure the bit error rate (BER). According to the specifications, fast interfaces such as USB or PCI Express typically have a target BER of ten to twelve. This means that only one incorrectly transmitted bit is allowed for every sequence of 1012 bits. However, validating the total jitter with a BER tester is very time consuming and does not provide any details about the individual jitter components.
The Jitter Separation Was Invented
Oscilloscopes are unsuitable for direct BER measurements due to their limited acquisition memory inside the measuring device. A straightforward measurement of the total jitter for a certain BER is impossible, as illustrated in the following example.
The waveform acquisition time for a test pattern with 1012 bits is 200 seconds at a data rate of 5 Gbit/s. With a sampling rate of 20 Gsample/s, an acquisition memory of four Tsample would be required. Today’s oscilloscopes do not have such a deep acquisition memory.
In the early 2000s, a smart solution to this dilemma was found: the invention of jitter separation (also known as jitter decomposition) and the subsequent estimation of the total jitter. The idea behind this approach is that the total jitter consists of deterministic components and random components.
The deterministic jitter is bounded, while the random jitter is unbounded and therefore its peak-to-peak values scale with the BER. Fig. 2 shows these jitter components in the BER bathtub curve. The open eye area for data sampling by the receiver is the difference between the unit interval (UI) and the total jitter (TJ).
The Jitter Components and Their Causes
Deterministic jitter can be broken down into several components: data dependent jitter, periodic jitter and other bounded uncorrelated jitter components (Fig. 2). Understanding the dominating jitter components in a signal enables developers to take suitable measures to optimize the design.
Jitter components have various causes:
- Random jitter (RJ) depends on factors such as the quality of the reference clock oscillator or the thermal noise of semiconductor components
- Periodic jitter (PJ) is typically caused by interferers from switched-mode power supplies or oscillators, or is a sign of PLL stability issues
- Intersymbol interference (ISI) is mainly related to transmission losses and limited bandwidth of circuits and signal transmission paths, including reflections caused by impedance mismatches
- Duty cycle distortion, which is the other part of data dependent jitter, indicates rise/fall time mismatches of the signal edges or offset errors in the transmitter or receiver
- Bounded uncorrelated jitter is typically caused by crosstalk from adjacent signal traces
These examples show that jitter decomposition is an important first step for localizing design problems and achieving cost-effective solutions.
A New Algorithm for Jitter Decomposition
The approaches and algorithms for jitter decomposition have evolved over the last 20 years. The initial methods such as tail fitting for determining random jitter and the dual Dirac model for estimating deterministic jitter, are still being used and are included in certain interface specifications. The conventional method to further break down the deterministic jitter reduces the input signal information from the sampling points of an analog waveform to a set of time interval error (TIE) measurements (Fig. 3).
The new jitter decomposition algorithm from Rohde & Schwarz uses an analytical approach. It is based on a parametric signal model that fully characterizes the behavior of the transmission path under test (Fig. 4). The main advantage of this method is that it utilizes the complete waveform characteristic, including the vertical and horizontal components. This leads to more accurate and more consistent measurement results, even for relatively short signal sequences. The core element of the signal model is the step response that describes the data dependent characteristics of the signal. The model also includes the periodic and random error terms (Fig. 4).
During the decomposition process, a least square (LS) estimator compares the input signal to the signal model and iteratively calculates the parameters of the signal model. Then, based on the input signal’s bit sequence, the algorithm reconstructs synthetic signal sequences for the individual deterministic jitter components (Fig. 5). In the next step, the random jitter is calculated from the difference between the input signal and the data dependent and periodic synthetic signal sequences.
Get a Deep Insight Into the Jitter Characteristic
The characteristic step response that results from the jitter composition calculation is new and very useful for debugging and optimizing designs (Fig. 6). Previously the step response could only be measured with time domain transmissometry (TDT) or with a vector network analyzer. The step response says a lot about the characteristics of the transmission path. For instance: the rise time is related to the bandwidth, overshoots or a damped response provide information about the frequency response characteristics, and dips indicate reflections due to mismatches.
The algorithm provides information about all common jitter components. Users can analyze the various components as numerical values or examine them in histograms, track curves or spectrum views. BER bathtub curves and eye diagrams support in-depth analysis.
The Rohde & Schwarz signal model differentiates between the horizontal and vertical direction of periodic jitter compontents (Fig. 7a + 7b). The direction provides useful information about whether periodic jitter components originate from amplitude modulation or frequency modulation. The spectrum of the horizontal periodic jitter components is available for analysis.
Quick Start for Analysis or Custom Setup in Three Steps
The new decomposition algorithm is integrated into the R&S RTO/RTP-K133 advanced jitter analysis option for the R&S RTO and R&S RTP oscilloscopes. The quick start function is the easiest route to fast jitter results. It automatically performs predefined setups, calculates a default set of jitter components and displays the corresponding results in preselected views. Users can adjust the setup and the result display at any time. As an alternative to quick start, users can custom configure a setup in just three steps. The first step is to select the signal source and type and define the clock data recovery (CDR). A selection menu for the DUT technology (e.g. USB 3.1 Gen 1) simplifies the CDR setup.
The second step is to configure the parameters for decomposition. This consists of selecting the jitter components of interest and defining the step response length for processing. A longer length uncovers more details, such as far away reflections, but it requires more computation time. The final step is configuring the result display. For the jitter components, the user can choose between the histogram, track and spectrum views. The step response, the bathtub curve and the synthetic eye diagram are available for in-depth analysis. Now the user simply has to press the Enable button to start the jitter decomposition process. The R&S SmartGrid function allows users to arrange the screen to their preference by simply dragging and dropping diagrams and tables.
Conclusion: The new jitter decomposition algorithm calculates the step response, which fully characterizes the deterministic behavior of the transmission path. Users benefit from more accurate measurement results – even for relatively short signal sequences. The in-depth results give developers deep insights for validating and debugging DUTs with high speed data interfaces or fast clock signals.